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?  part temp range pin-package ds2431+ -40c to +85c 3 to-92 ds2431+t&r -40c to +85c 3 to-92 ds2431p+ -40c to +85c 6 tsoc ds2431p+t&r -40c to +85c 6 tsoc ds2431g+ -40c to +85c 2 sfn ds2431g+t&r -40c to +85c 2 sfn ds2431q+t&r -40c to +85c 6 tdfn-ep* (2.5k pcs) ds2431x-s+ -40c to +85c 3x3 ucspr (2.5k pcs) ds2431x+ -40c to +85c 3x3 ucspr (10k pcs) available evaluation kit available ?????????????? ? ????? maxi m? 1080 0 85 2 124 9 () 1080 0 15 2 124 9 ( ) maxi m?china.maximintegrated.com ds2431
2135?2.xjsf! ffqspn absolute maximum ratings electrical characteristics (t a = -40c to +85c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. io voltage range to gnd .......................................-0.5v to +6v io sink current ...................................................................20ma operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-55c to +125c lead temperature (excluding ucsp, soldering, 10s).....+300c soldering temperature (reflow) to-92 ............................................................................+250c ail other packages, excluding sfn ..............................+260c parameter symbol conditions min typ max units io pin: general data 1-wire pullup voltage v pup (note 2) 2.8 5.25 v 1-wire pullup resistance r pup (notes 2, 3) 0.3 2.2 k  input capacitance c io (notes 4, 5) 1000 pf input load current i l io pin at v pup 0.05 6.7 a high-to-low switching threshold v tl (notes 5, 6, 7) 0.5 v pup - 1.8 v input low voltage v il (notes 2, 8) 0.5 v low-to-high switching threshold v th (notes 5, 6, 9) 1.0 v pup - 1.0 v switching hysteresis v hy (notes 5, 6, 10) 0.21 1.70 v output low voltage v ol at 4ma (note 11) 0.4 v standard speed, r pup = 2.2k  5 overdrive speed, r pup = 2.2k  2 recovery time (notes 2,12) t rec overdrive speed, directly prior to reset pulse; r pup = 2.2k  5 s standard speed 0.5 5.0 rising-edge hold-off time (notes 5, 13) t reh overdrive speed not applicable (0) s standard speed 65 time slot duration (notes 2, 14) t slot overdrive speed 8 s io pin: 1-wire reset, presence-detect cycle standard speed 480 640 reset low time (note 2) t rstl overdrive speed 48 80 s standard speed 15 60 presence-detect high time t pdh overdrive speed 2 6 s standard speed 60 240 presence-detect low time t pdl overdrive speed 8 24 s standard speed 60 75 presence-detect sample time (notes 2, 15) t msp overdrive speed 6 10 s ds2431 2 maxim integrated
2135?2.xjsf! ffqspn electrical characteristics (continued) (t a = -40c to +85c.) (note 1) parameter symbol conditions min typ max units io pin: 1-wire write standard speed 60 120 overdrive speed, v pup > 4.5v 5 15.5 write-zero low time (notes 2, 16, 17) t w0l overdrive speed 6 15.5 s standard speed 1 15 write-one low time (notes 2, 17) t w1l overdrive speed 1 2 s io pin: 1-wire read standard speed 5 15 -  read low time (notes 2, 18) t rl overdrive speed 1 2 -  s standard speed t rl +  15 read sample time (notes 2, 18) t msr overdrive speed t rl +  2 s eeprom programming current i prog (notes 5, 19) 0.8 ma programming time t prog (notes 20, 21) 10 ms at +25c 200k write/erase cycles (endurance) (notes 22, 23) n cy at +85c (worst case) 50k  data retention (notes 24, 25, 26) t dr at +85c (worst case) 40 years note 1: specifications at t a = -40c are guaranteed by design only and not production tested. note 2: system requirement. note 3: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2482-x00, ds2480b, or ds2490 may be required. note 4: maximum value represents the internal parasite capacitance when v pup is first applied. if a 2.2k resistor is used to pull up the data line, 2.5s after v pup has been applied, the parasite capacitance does not affect normal communications. note 5: guaranteed by design, characterization, and/or simulation only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage, which is a function of v pup , r pup , 1-wire timing, and capacitive loading on io. lower v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on io, a logic 0 is detected. note 8: the voltage on io must be less than or equal to v ilmax at all times the master is driving io to a logic 0 level. note 9: voltage above which, during a rising edge on io, a logic 1 is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io must drop by at least v hy to be detected as logic 0. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: applies to a single device attached to a 1-wire line. note 13: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 14: defines maximum possible bit rate. equal to t w0lmin + t recmin . note 15: interval after t rstl during which a bus master is guaranteed to sample a logic 0 on io if there is a ds2431 present. minimum limit is t pdhmax ; maximum limit is t pdhmin + t pdlmin . note 16: numbers in bold are not in compliance with legacy 1-wire product standards. see the comparison table. note 17: in figure 11 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 18: in figure 11 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input-high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . ds2431 3 maxim integrated 3
note 19: current drawn from io during the eeprom programming interval. the pullup circuit on io during the programming interval should be such that the voltage at io is greater than or equal to v pupmin . if v pup in the system is close to v pupmin , a low- impedance bypass of r pup , which can be activated during programming, may need to be added. note 20: interval begins t rehmax after the trailing rising edge on io for the last time slot of the e/s byte for a valid copy scratchpad sequence. interval ends once the devices self-timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l . note 21: t prog for units branded version a1 is 12.5ms. t prog for units branded version a2 and later is 10ms. note 22: write-cycle endurance is degraded as t a increases. note 23: not 100% production tested; guaranteed by reliability monitor sampling. note 24: data retention is degraded as t a increases. note 25: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. note 26: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-term storage at elevated tem- peratures is not recommended; the device can lose its write capability after 10 years at +125c or 40 years at +85c. m- legacy values ds2431 values standard speed (s) overdrive speed (s) standard speed (s) overdrive speed (s) parameter min max min max min max min max t slot (including t rec ) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined) t rstl 480 (undefined) 48 80 480 640 48 80 t pdh 15 60 2 6 15 60 2 6 t pdl 60 240 8 24 60 240 8 24 t w0l 60 120 6 16 60 120 6 15.5 2135?2.xjsf! ffqspn * ?@ ?r|? ??? ? ? ?2.xjsf? ??|
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2135?2.xjsf! ffqspn bus master tx memory function command bus master tx ta1 (t[7:0]), ta2 (t[15:8]) bus master rx ta1 (t[7:0]), ta2 (t[15:8]), and e/s byte bus master rx data byte from scratchpad master tx data byte to scratchpad applies only if the memory area is not protected. if write protected, the ds2431 copies the date byte from the target address into the scratchpad. if in eprom mode, the ds2431 loads the bitwise logical and of the transmitted byte and the data byte from the targeted address into the scratchpad. bus master rx "1"s ds2431 increments e[2:0] pf = 0 ds2431 sets pf = 1 clears aa = 0 sets e[2:0] = t[2:0] 0fh write scratchpad? n y n y n y y y n n master tx reset? e[2:0] = 7? t[2:0] = 0? master tx reset? ds2431 sets scratchpad byte counter = t[2:0] aah read scratchpad? n y ds2431 tx crc-16 of command, address, and data bytes as they were sent by the bus master bus master rx "1"s y n master tx reset? bus master rx crc-16 of command, address, e/s byte, and data bytes as sent by the ds2431 y n master tx reset? y byte counter = e[2:0]? from rom functions flowchart (figure 9) to rom functions flowchart (figure 9) ds2431 increments byte counter n to figure 7b from figure 7b d8b/! @ ? d ds2431 10 maxim integrated
2135?2.xjsf! ffqspn bus master tx ta1 (t[7:0]), ta2 (t[15:8]) applicable to all r/w memory locations. duration: t prog * * 1-wire idle high for power. ds2431 copies scratchpad data to address bus master rx "1"s aa = 1 bus master rx "1"s master tx reset? n y n n master tx reset? y master tx reset? bus master tx ta1 (t[7:0]), ta2 (t[15:8]) and e/s byte 55h copy scratchpad? n y y y n ds2431 tx "0" ds2431 tx "1" f0h read memory? n y y n auth. code match? y n y n n t[15:0] < 0090h? pf = 0? address < 90h? y copy protected? bus master rx "1"s master tx reset? n y ds2431 sets memory address = (t[15:0]) bus master rx data byte from memory address y n n master tx reset? address < 8fh? n y master tx reset? ds2431 increments address counter y to figure 7a from figure 7a d8c/! @ ? d)?* ds2431 11 maxim integrated 11
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2135?2.xjsf! ffqspn ds2431 tx presence pulse bus master tx reset pulse bus master tx rom function command ds2431 tx crc byte ds2431 tx family code (1 byte) ds2431 tx serial number (6 bytes) rc = 0 master tx bit 0 rc = 0 rc = 0 rc = 0 od = 0 y y y y y y y y 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? od reset pulse? n n cch skip rom command? n rc = 1 master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y rc = 1 from memory functions flowchart (figure 7) to memory functions flowchart (figure 7) ds2431 tx bit 0 ds2431 tx bit 0 master tx bit 0 bit 1 match? bit 63 match? ds2431 tx bit 1 ds2431 tx bit 1 master tx bit 1 ds2431 tx bit 63 ds2431 tx bit 63 master tx bit 63 y to figure 9b to figure 9b from figure 9b from figure 9b d:b/! spn ? d ds2431 14 maxim integrated
2135?2.xjsf! ffqspn rc = 0; od = 1 rc = 0; od = 1 n bit 0 match? y n rc = 1? y a5h resume command? n y 3ch overdrive- skip rom? n y 69h overdrive- match rom? from figure 9a from figure 9a to figure 9a to figure 9a n y y n master tx reset? y master tx reset? n bit 1 match? master tx bit 0 master tx bit 1 od = 0 n od = 0 n od = 0 y rc = 1 bit 63 match? master tx bit 63 y d:c/! spn ? d)?* ds2431 15 maxim integrated 15
2135?2.xjsf! ffqspn sftvnf! \b6i^ ? ?"mt ??
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a ? . ?r??? o resistor master ds2431 t rstl t pdl t rsth t pdh master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp d21/! ?*
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2135?2.xjsf! ffqspn resistor master resistor master resistor master ds2431 v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slot write-zero time slot read-data time slot d22/! 0v?d ds2431 18 maxim integrated
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38 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 16 + x 15 + x 2 + 1 input data crc output x 5 x 6 11th stage 12th stage 15th stage 14th stage 13th stage x 11 x 12 9th stage 10th stage x 9 x 10 x 13 x 14 x 7 16th stage x 16 x 15 x 8 d24/! dsd.27n h?
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s- symbol description rst 1-wire reset pulse generated by master. pd 1-wire presence pulse generated by slave. select command and data to satisfy the rom function protocol. ws command "write scratchpad." rs command "read scratchpad." cps command "copy scratchpad." rm command "read memory." ta target address ta1, ta2. ta-e/s target address ta1, ta2 with e/s byte. <8Ct[2:0] bytes> transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. transfer of as many data bytes as are needed to reach the end of the memory. crc-16 transfer of an inverted crc-16. ff loop indefinite loop where the master reads ff bytes. aa loop indefinite loop where the master reads aa bytes. programming data transfer to eeprom; no activity on the 1-wire bus permitted during this time. ds2431 20 maxim integrated
2135?2.xjsf! ffqspn `````````````````````````````````````````````````` ? ? 2.xjsf0gog h? i ``````````````````````````````````````````````````````````````` `````` 2.xjsf0g, ? master to slave slave to master programming write scratchpad (cannot fail) rst pd select ws ta <8Ct[2:0] bytes> crc-16 ff loop read scratchpad (cannot fail) rst pd select rs ta-e/s <8Ct[2:0] bytes> crc-16 ff loop copy scratchpad (success) rst pd select cps ta-e/s programming aa loop copy scratchpad (invalid address or pf = 1 or copy protected) rst pd select cps ta-e/s ff loop read memory (success) rst pd select rm ta ff loop read memory (invalid address) rst pd select rm ta ff loop ds2431 21 maxim integrated 21
2135?2.xjsf! ffqspn ````````````````````````` @ ?, ? v?@?2|9 
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-??,? master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 20h ta1, beginning offset = 20h tx 00h ta2, address = 00 20h tx <8 data bytes> write 8 bytes of data to scratchpad rx <2 bytes crc-16 > read crc to check for data integrity tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 20h read ta1, beginning offset = 20h rx 00h read ta2, address = 00 20h rx 07h read e/s, ending offset = 111b, aa, pf = 0 rx <8 data bytes> read scratchpad data and verify rx <2 bytes crc-16 > read crc to check for data integrity tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 20h ta1 tx 00h ta2 tx 07h e/s (authorization code) <1-wire idle high> wait t progmax for the copy function to complete rx aah read copy status, aah = success tx (reset) reset pulse rx (presence) presence pulse tx cch issue skip rom command tx f0h issue read memory command tx 00h ta1, beginning offset = 00h tx 00h ta2, address = 00 00h rx <144 data bytes> read the entire memory tx (reset) reset pulse rx (presence) presence pulse ds2431 22 maxim integrated
2135?2.xjsf! ffqspn 2 3 1 2 3 1 3 2 1 n.c. io gnd to-92 top view n.c. io gnd n.c. n.c. n.c. tsoc + 5 4 6 2 3 1 ds2431 sfn (6mm 6mm 0.9mm) bottom view note: the sfn package is qualified for electro-mechanical contact applications only, not for soldering. for more information, refer to application note 4132: attachment methods for the electro-mechanical sfn package. 12 io gnd side view front view (t&r version) front view side view ds2431 ucspr top view gnd n.c. n.c. a1 a2 a3 c1 c2 c3 io n.c. n.c. 16 n.c. n.c. 25 io n.c. 34 gnd n.c. tdfn-ep (3mm 3mm) top view ds2431 2431 ymrrf + *ep *exposed pad ```````````````````````````````````````````````````````````````````````````` [ m|? ds2431 23 23 maxim integrated
2135?2.xjsf! ffqspn user direction of feed leads face up in orientation shown above. ``````````````````````````````````````````````````````````````` tgo v?? r?|?? v? o v? i jp
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g? ds2431 ma xim ma xim ??????? ? max im ????????? ? ???(??)?????? maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 26 ? 201 maxim integrated maxim?maxim integratedmaxim integrated products, inc.?? maxim 8328 100083 ?800 810 0310 010-6211 5199 010-6211 5299


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